Apparatus for vehicular traffic intersection controllers



April 28, 1970 D. ARLEN ETAL APPARATUS FOR VEHICULAR TRAFFICINTERSECTION CONTROLLERS Filed Oct.. 3. 1967 A FREE -1- K FREE FLIP-FLOP$10 8w FLIP- FLOP 1 o 1 o I I LOAD x 6 CFLREEAER x A\ V A x 7 \T/ X F-SZ 5 FLIP-FLOP 0 A o FREE SWITCH FREE START LIGHT TRAFFIC OFFSET COMMANDINVENTORS DAV/D APLE/V JOHN J. KING ATTORNEY United States Patent US.Cl. 34036 5 Claims ABSTRACT OF THE DISCLOSURE Apparatus for trafiicintersection controllers when the controller transfers to, operates in,or transfers from a rvon-coodinated or free mode of operation whichassures that the major traffic phase is accorded with a minimumright-of-way interval for each non-coordinated cycle as well as duringthe transition period.

BACKGROUND OF THE INVENTION Field of the invention The present inventionpertains to apparatus for traflic intersection controllers of thesemi-actuated type for providing proper actuation during conditions oflight tratfic density as well as during transition periods.

Description of the prior art In a coordinated traffic control system,the local intersection controllers in a section operate with the samebackground cycle and with a particular set of offset values depending onthe density of traflic. When the traffic density changes, the centralcontroller changes the set of offset values on which the controllers inthe section operate. For a particular offset value, a controller in thesection has a preset time during the background cycle at which toinitiate its local cycle. Some controllers in the section are of thenon-actuated variety; that is, they continuously effectuate a localcycle in accordance with the background cycle and the selected localoffset values. Other controllers in the section are of the semi-actuatedtype; that is, they continuously display a green indication for themajor trafiic phase and a red indication for the itnersecting trafficphases until a local actuation is received from a vehicle or apedestrian. The controller then waits for its coordinated preset time inthe background cycle to initiate a local cycle. The semi-actuatedcontroller initiates local cycles only when demanded and they are timedin accordance with the background cycle and the selected cal offsetvalue.

During conditions of light trafiic density, it is often desirable tofree the semi-actuated controller from the requirement to wait for apreset time in the background cycle to initiate its local cycle. Itwould be advantageous, under these circumstances, to initiate the cycleimmediately upon receipt of an actuation. Thus, semi-actuatedcontrollers are provided with a two-position switch for selecting thecoordinated or the free condition for the local operation mode. When theswitch is positioned to select the free mode, the controller operates inthe coordinated mode until the central controller selects the lighttraffic olrst values for the section. At this time, the controllercommences to operate in the free mode. When the tratfic densityincreases so as to cause the central controller to select other than thelight trafl'ic offset values, the controller reverts to the coordinatedmode of operation.

When operating in a free mode, a semi-actuated controller times a localcycle in response to an actuation and thereafter remains in a restinterval until receipt of another actuation. During the rest interval, agreen indication is displayed to the main tratfic phase. Should traificon the secondary phase be continuous, the controller would continuallyexecute local cycles remaining in the rest interval only momentarily.Thus the right-of-way would be continuously accorded to the secondaryphase and only momentarily to the main phase. Therefore, any vehiclearriving at the intersection on the major phase would have to wait untilall of the vehicles on the secondary phase have cleared the intersectionbefore proceeding.

To avoid this anomalous condition, when operating in the free mode,controllers at attaining the rest interval after executing a localcycle, insert an interval which accords the right-of-way to the majortraffic phase for a preset duration before reverting'to vehicle passageon the secondary phase. Thus, despite the traffic density on thesecondary phases, the right-of-way will be given to the major phase oncefor each cycle executed when operating in the free mode.

When operating in either the coordinated or the noncoordinated mode,controllers operate properly. However, when executing the transitionbetween modes, the transitional cycle may be severely distorted. Forexample, a controller operating in the free mode, when entering thedwell interval after executing a local cycle, begins to display theright-of-way signal to the major phase. If at this time, the command torevert to the coordinated mode is received and the signal to begin acoordinated local cycle is also received, the right-of-way for the majorphase may be abruptly terminated. Vehicles waiting on the major phaseand vehicles arriving on the secondary phase may, under thesecircumstances, enter the intersection simultaneously with potentiallycatastrophic results.

SUMMARY OF THE INVENTION The present invention overcomes the problemsexplained above by providing in a semi-actuated intersection controllerresponsive to mode signals, the means for timing an interval includinginhibiting means effective to inhibit initiation of a non-coordinatedcycle until the interval is timed and initializing means for actuatingthe timing means at the coincidence of a non-coordinated mode commandsignal and the dwell interval of the controller cycle as well as controlmeans for actuating the timing means once for each initiatednon-coordinated cycle and means for inhibiting the termination of thenon-coordinated mode when the timing means are activated.

BRIEF DESCRIPTION OF THE DRAWINGS The single drawing is a schematicdiagram of the apparatus incorporating the present invention applied toa semi-actuated traffic intersection controller.

DESCRIPTION OF THE PREFERRED EMBODIMENT The present invention will bedescribed for purposes of exaihple with respect to the semi-actuatedtype of trafiic intersection controller of the character explained inUS. patent application Ser. No. 453,072 now abandoned entitled TralficIntersection and Other Signal Controllers Responsive to a Cyclic PulseTrain, filed May 4, 1965 in the name of John J. King which may be usedin conjunction witlfa system of the type described in US. patentapplication Ser. No. 452,974 now abandoned entitled Control System forControlling Vehicular Traffic Flow or Other Moving Elements, filed May4, 1965 in the name of John J. King et al.

The present invention provides apparatus for use in a semi-actuated typeof intersection controller responsive to command signals representativeof various traffic densities at the local intersection which cantransfer between system modes predetermined and selectable parameterswhile maintaining synchronism with the individual intersection cycle.The system operation of the semi-actuated controller is such that itmust be capable of operating interchangeably between three system modes,i.e., the coordinated mode, the free mode and the standby mode. Further,the central site may be capable of switching between two of these modes,such as the coordinated and free modes by means of communication commandsignals.

In the coordinated mode of operation, the local intersection cycle of aparticular controller, i.e., the transferring of green time from onestreet to the other is determined by a combination of switch settings onthe switch panel of the local controller and the communicationinformation received from the central site, i.e., offset command, splitcommand, background start and cycle length, as explained in detail insaid patent applications S.N. 452,- 974 and 453,072. In the free mode,the local controller uses a combination of switch settings, differentfrom those used in the coordinated mode, to determine the localintersection cycle. The controller also uses less communicationinformation than in the coordinated mode, i.e., spli-t command and cycleinformation. The controller is also more responsive to localintersection trafiic in the free mode than in the coordinated mode;rather than being capable of responding to traffic calls for of thecycle as in the coordinated mode, the controller can now respond at anypoint within the cycle.

In a particular controller, the conditions required for free modeoperation are that the free switch be in the ON position, and that it beoperating on a light trafiic offset command. The free switch is usuallyset when the controller is installed at a particular intersection. Theoffset communication from the central site usually connects to numerouslocal intersection controllers. Then, when the central site changes tolight traffic offset command, the individual intersection controllersare in different portions of their local intersection cycle. Thus, thetransferring to the free mode can be random in its occurrence withrespect to an individual local intersection cycle. Conversely, the samewill be true when transferring out of the free mode.

Inconsistencies may occur during the transitional period because of themeshing of the two types of local intersection cycles which among otherthings can cause a disjointed local intersection cycle. Also in thetransitional period, the major phase green time changes from a constant(switch settable) to a variable function of the local intersectiontraffic density that can under certain conditions reduce to zero.

The present invention overcomes the aforementioned problems byestablishing two conditions for the controllers response during thetransitional period. First, the transfer of operation takes place beforethe beginning of the next local intersection cycle, and second, themajor phase green time during the transition is a minimum value settablethrough a controller panel switch. The circuit shown in the drawingsatisfies these conditions.

Referring now to the drawing, the operation of the present inventionwill be explained first with respect to the transition of the controllerto the free mode of operation. The free switch 1 is in the ON positionas shown. The light traffic offset command is received from the centralsite on four communication lines connected to an AND gate 2. The lighttraffic offset command enables the AND gate 2. The next background startsignal S* will guide the received signal through gating to set atransition memory cell in a manner to be explained. The 8* signal isgenerated by the background start pulse as described in said US. patentapplication S.N. 453,072. An AND gate 3 is then enabled with all itsinput terminals energized since the free switch 1 is in the ON position,the controller is not yet in the free mode thereby providing a m signal,the 8* signal is present and there is an output from the AND gate 2. Theoutput of the AND gate 3 enables an OR gate 4 which sets the transitionmemory cell FREE START (F.S.) flip-flop 5. This is kept in thetransition memory cell 5 until the local intersection cycle of thecontroller is finished. Then a minimum green period, as set on the A MINswitch (not shown) is timed out by the controllers interval counter (notshown), all as explained in said US. patent application S.N. 453,072.The A MIN switch determines the minimum major phase green time. At theend of the minimum green period timing, the mode memory cell FREEflip-flop 8 is set.

The controller contains an oscillator (not shown) which generates fourclock time pulses, i.e., w, x, y and z clock times, each separated by 50microseconds which are utilized in the present invention. The controlleralso has the interval counter mentioned above cooperative with asequencing unit (not shown) but fully explained in said US. patentapplication S.N. 453,072 which provides sequential interval signalsdesignated by Roman numerals such as I to X. At interval X, whichrepresents the major phase green, and the next 2 clock time, an AND gate6 is enabled by being responsive to the X and z signals and to thebinary ONE output of the RS. flip-flop 5. The output of the AND gate 6generates a clear free signal. This signal clears the interval counterto its initial or ZERO value and sets the mode memory cell FREEflip-flop 8.

At the next x clock time, an AND gate 7 which is responsive to theinterval X signal, the x signal and the binary ONE output of the RS.flip-flop 5 is enabled. The output of the AND gate 7 sets a K flip-flop10 and generates a load signal which loads the switch setting into thecontrollers interval counter. This load signal performs the samefunction as the insert data signal of said US. patent application S.N.453,072. The time that the K flipflop 10 remains set is equal to theinterval counter counting period.

At the next y clock time, an AND gate 11 which is responsive to thebinary ONE output of the K flip-flop 10, the binary ONE output of theFREE flip-flop 8 and to the y signal is enabled. The AND gate 11 outputresets the RS. flip-flop 5 through an OR gate 12.

When the A MIN period has been timed out by the interval counter, a C3pulse is generated which resets the K flip-flop 10. The controller nowoperates in the free operation.

A traffic call will immediately start the controller in its local cycle.If a call is received by the controller, the

'+V' line will be enabled to provide a signal accordingly. The P'+ Vsignal enables an AND gate 15 which is also responsive to the binaryZERO signals from the RS. and K flip-flops 5 and 10, respectively, aswell as the interval X signal, the w signal and the binary ONE signalfrom the FREE flip-flop 8. The output of the AND gate 15 generates thefree start signal. The free start signal enables OR gate 22, whose otherinput is the output of the AND gate of said US. patent application Ser.No. 453,072. The AND gate 105 is responsive to a binary zero signal fromthe FREE flip-flop 8, the IX interval signal, and the A signal. Thefunctions performed by the output of the AND gate 105, as discussed insaid US. patent application Ser. No. 453,072, are now performed by theoutput of the OR gate #22; namely, starting the controller sequencingthrough its local cycle. Then at this time, the circuit has placed thecontroller in the free mode.

An AND gate 16 is utilized while operating in the free mode. The ANDgate 16 is responsive to the C3, interval VIII and the binary ONE outputof the FREE flip-flop 8. When the AND gate 16 is enabled, the ES.flip-flop 5 is set through the OR gate 4. The operation as describedabove with respect to the z clock pulse is repeated to satisfy theoperating requirements while in this mode.

The transition of the controller from the free mode will now bedescribed. First, the offset command is changed on the input lines tothe AND gate 2. With the controller sequencing through its local cycle,the change in offset command will be stored in the transitional memorycell F.S. flip-flop 5 at the next background start.

However, if the A MIN period is timed out before the next backgroundstart, the controller will switch out of the mode at that time thusremoving the need for storage in the transitional memory cell 5. The ANDgate 2 is disabled by the change in the offset command. With thecontroller timing the A MIN period, the interval X line is enabled. Atthe end of the period, a C3 signal is generated which enables an ANDgate 17 that is responsive to the interval X signal, the C3 signal andthe inverted output of the AND gate 2 via an inverting circuit 18. Theoutput of the AND gate 17 is connected through an OR gate 20 to resetthe FREE flip-flop 8. Thus, the controller is switched back to thecoordinated mode.

When the next background start occurs before the previous step (nottiming A MIN period), an AND gate 21 is enabled which sets the ES.flip-flop 5 through the OR gate 4. Then the same sequence for the RS.flip-flop 5, as described before, will be repeated except now at the C3signal, the AND gate 17 will be enabled. This will switch the controllerto the coordinated mode.

An advantage of the present invention lies in the fact that itincorporates both the functions required during the free mode and theconditions required during the transition between modes therebyminimizing the structure required to perform these functions.

We claim:

1. In a semi-actuated master controlled trafiic intersection controlleradapted to operate selectively in coordinated and non-coordinated modes,

means responsive to command signals from a master controller commandingoperation in said non-coordinated mode,

timing means for timing an interval including inhibiting means effectiveto inhibit initation of a noncoordinated cycle until said interval istimed, initializing means for actuating said timing means at the firstoccurring coincidence of said non-coordinated mode command signal and asignal indicating that the intersection controller is green in the majortrafiic phase, control means for actuating said timing means once foreach non-coordinated cycle initiated, and

means for inhibiting the termination of said noncoordinated mode whensaid timing means are activated.

2. In a controller of the character recited in claim 1 and furtherincluding means for inserting said interval when transferring fromnon-coordinated to coordinated operation.

3. In a controller of the character recited in claim 1 wherein saidmeans for inhibiting the termination of said non-coordinated mode whensaid timing means are activated includes a non-coordinated mode memoryflip-flop.

4. In a controller of the character recited in claim 1 in which saidinterval is the minimum right-of-way interval for the major trafiicphase.

5. In a controller of the character recited in claim 1 in which thenon-coordinated command signal is the coincidence between the actuatedposition of the free switch and the light traflic offset command fromthe master controller.

References Cited UNITED STATES PATENTS 10/1955 Jetfers 340--37 6/1966Lesher 34035 US. Cl. X.R. 340-37, 40

